# Intel(r) Wireless MMX(tm) technology testcase for WALIGNR
# mach: xscale
# as: -mcpu=xscale+iwmmxt

	.include "testutils.inc"

	start

	.global walignr
walignr:
	# Enable access to CoProcessors 0 & 1 before
        # we attempt these instructions.

	mvi_h_gr   r1, 3
	mcr        p15, 0, r1, cr15, cr1, 0

	# Test 0 byte align
	
	mvi_h_gr   r0, 0x12345678
	mvi_h_gr   r1, 0x9abcdef0
	mvi_h_gr   r2, 0x11111111
	mvi_h_gr   r3, 0x00000000
	mvi_h_gr   r4, 0
	mvi_h_gr   r5, 0
	mvi_h_gr   r6, 3

	tmcrr	   wr0, r0, r1
	tmcrr	   wr1, r2, r3
	tmcrr	   wr2, r4, r5
	tmcr	   wcgr0, r6

	walignr0   wr2, wr0, wr1
	
	tmrrc	   r0, r1, wr0
	tmrrc	   r2, r3, wr1
	tmrrc	   r4, r5, wr2
	tmrc	   r6, wcgr0
	
	test_h_gr  r0, 0x12345678
	test_h_gr  r1, 0x9abcdef0
	test_h_gr  r2, 0x11111111
	test_h_gr  r3, 0x00000000
	test_h_gr  r4, 0xbcdef012
	test_h_gr  r5, 0x1111119a
	test_h_gr  r6, 3

	# Test 1 byte align
	
	mvi_h_gr   r0, 0x12345678
	mvi_h_gr   r1, 0x9abcdef0
	mvi_h_gr   r2, 0x11111111
	mvi_h_gr   r3, 0x00000000
	mvi_h_gr   r4, 0
	mvi_h_gr   r5, 0
	mvi_h_gr   r6, 4

	tmcrr	   wr0, r0, r1
	tmcrr	   wr1, r2, r3
	tmcrr	   wr2, r4, r5
	tmcr	   wcgr1, r6

	walignr1   wr2, wr0, wr1
	
	tmrrc	   r0, r1, wr0
	tmrrc	   r2, r3, wr1
	tmrrc	   r4, r5, wr2
	tmrc	   r6, wcgr1
	
	test_h_gr  r0, 0x12345678
	test_h_gr  r1, 0x9abcdef0
	test_h_gr  r2, 0x11111111
	test_h_gr  r3, 0x00000000
	test_h_gr  r4, 0x9abcdef0
	test_h_gr  r5, 0x11111111
	test_h_gr  r6, 4

	# Test 2 byte align
	
	mvi_h_gr   r0, 0x12345678
	mvi_h_gr   r1, 0x9abcdef0
	mvi_h_gr   r2, 0x11111111
	mvi_h_gr   r3, 0x00000000
	mvi_h_gr   r4, 0
	mvi_h_gr   r5, 0
	mvi_h_gr   r6, 2

	tmcrr	   wr0, r0, r1
	tmcrr	   wr1, r2, r3
	tmcrr	   wr2, r4, r5
	tmcr	   wcgr2, r6

	walignr2   wr2, wr0, wr1
	
	tmrrc	   r0, r1, wr0
	tmrrc	   r2, r3, wr1
	tmrrc	   r4, r5, wr2
	tmrc	   r6, wcgr2
	
	test_h_gr  r0, 0x12345678
	test_h_gr  r1, 0x9abcdef0
	test_h_gr  r2, 0x11111111
	test_h_gr  r3, 0x00000000
	test_h_gr  r4, 0xdef01234
	test_h_gr  r5, 0x11119abc
	test_h_gr  r6, 2

	# Test 3 byte align
	
	mvi_h_gr   r0, 0x12345678
	mvi_h_gr   r1, 0x9abcdef0
	mvi_h_gr   r2, 0x11111111
	mvi_h_gr   r3, 0x00000000
	mvi_h_gr   r4, 0
	mvi_h_gr   r5, 0
	mvi_h_gr   r6, 5

	tmcrr	   wr0, r0, r1
	tmcrr	   wr1, r2, r3
	tmcrr	   wr2, r4, r5
	tmcr	   wcgr3, r6

	walignr3   wr2, wr0, wr1
	
	tmrrc	   r0, r1, wr0
	tmrrc	   r2, r3, wr1
	tmrrc	   r4, r5, wr2
	tmrc	   r6, wcgr3
	
	test_h_gr  r0, 0x12345678
	test_h_gr  r1, 0x9abcdef0
	test_h_gr  r2, 0x11111111
	test_h_gr  r3, 0x00000000
	test_h_gr  r4, 0x119abcde
	test_h_gr  r5, 0x00111111
	test_h_gr  r6, 5

	pass
